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The 40 pins for instance of the Intel 8085 are allocated as follows: 8 pins 8 pins 9 pins 6 pins 2 2 3 2 40 pins pins pins pins pins address (output) multiplexed data/address (input/output) controlling of the buses (address latch enable, data bus status, read, write, ready, hold) interrupts and administration of interrupts serial I/O reset clock (input/output) power Different approaches are applied especially for CPU's. One objective requires integrating of all basic function elements like interfaces and memories (ROM and RAM) onto the CPU-chip in order to get "one-chip computers" (46, 47, 48, 49).

Nevertheless the definition, implementation and usage of an implementation language with a unique syntax for different processors is very important. For several widely-used processors BASIC and subsets of FORTRAN IV and for a growing number of processors also PASCAL (68) is offered. Extensions of these languages for real-time applications have been proposed and are already used (RT-BASIC (69), RTF0RTRAN (70) and Concurrent PASCAL ( 7 1 ) ) . However, the corresponding fact, as discussed for PL/M, can be recognized for these high-level languages which include for instance I/0-functions.

Only a few 8 - b i t processors ( e . g . Z80) o f f e r besides basic l o g i c - and load/storeinstructions special (high-level) i n s t r u c t i o n s f o r b i t - and s t r i n g - h a n d l i n g . Usually the addresses consist of 16 b i t s . The address registers and the program counter are 16 b i t s wide as w e l l . Therefore an address space up to 65 536 is d i r e c t l y available. The machine instructions for program control l i k e branch, conditional branch, subroutine c a l l , subroutine r e t u r n , increment and decrement (by one) e t c .

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